Most computer input/output (I/O) peripherals such as modems, keyboards, and cathode-ray-tube (CRT) terminals are serial in nature. As such, first-in-first-out (FIFO) buffers are used in serial interfaces, which are implemented between central processing unit (CPU) and serial I/O peripherals, to ensure that output data is always in the same order as input data. In addition, FIFO buffers are used to compensate for different transfer rates between the serial I/O peripherals and the central processing unit. In other words, a FIFO buffer can accept data from the source unit at one rate of transfer and deliver the data to the destination unit at another rate.
Currently, serial I/O peripherals are byte oriented. That is they transfer a byte of data at a time. However, recent advances in computer technology result in CPU that can support even higher serial data transfer rates such as two or more bytes at a time. To support higher serial data transfer rates, FIFO buffers with increased data storage capabilities are needed. Generally, the storage capability of a FIFO buffer can be increased by increasing the width of the FIFO buffer, increasing the depth of the FIFO buffer, or both. In increasing the storage capability of a FIFO buffer, system design constraints and associated costs are important considerations that may dictate the design. For example, a design having an increased FIFO depth may require a larger surface area than a design having an increased FIFO width resulting in a larger footprint, for the control logic and the data path combined, and consequently higher manufacturing costs. For this reason, it may be more desirable to increase the FIFO width rather than the FIFO depth in increasing the FIFO buffer storage capability.
However, increasing the FIFO buffer storage capacity by increasing the FIFO width creates challenges that must be overcome. One such challenge involves residual data bytes in the receive mode. Consider, as example, a synchronous serial interface uses to perform serial-to-parallel and parallel-to-serial data conversion. As data is serially received from the input port, it is shifted into a shift register which is normally sized to have the same bit-width (e.g., 2 bytes) as the FIFO buffer. The shift registers content is then loaded in parallel into the FIFO buffer prior to being sent to a destination. For improved bandwidth, the shift register is designed so that its content is sent to the FIFO buffer when it is filled with data.
Because the length of a message received is arbitrary, the shift register may not be filled at the end of a data message transfer. As a result, a number of residual data bytes may remain in the shift register at the end of a data message transfer because the shift register is not filled up. The shift register may also store residual data bytes if a data message transfer from the input port is interrupted leaving the shift register partially filled. In this case, the remaining message is sent to the shift register when data transfer resumes. Because the residual data bytes may represent the end of the data message which is not known at the time, the residual bytes need to be retrieved in both cases to avoid potential data loss.
In doing so, however, the residual data bytes may be retrieved twice in the case where the remaining data bytes are subsequently received following an interrupt. This can cause redundant data bytes in a data message which may cause confusion and lead to error conditions such as an incorrect data byte count during error detection.
Thus, a need exists for an arrangement, system, and method to allow residual data bytes to be retrieved effectively.